I. Field of the Disclosure
The technology of the disclosure relates generally to magneto-resistive random access memory (MRAM), and more particularly to performing access operations in MRAM bit cells in MRAM.
II. Background
Semiconductor storage devices are used in integrated circuits (ICs) in electronic devices to provide data storage. One example of a semiconductor storage device is magneto-resistive random access memory (MRAM). MRAM is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ) as part of an MRAM bit cell. One advantage of MRAM is that MTJs in MRAM bit cells can retain stored information even when power is turned off. This is because data is stored in the MTJ as a small magnetic element rather than as an electric charge or current.
In this regard, an MTJ comprises a free ferromagnetic layer (“free layer”) disposed above or below a fixed or pinned ferromagnetic layer (“pinned layer”). The free and pinned layers are separated by a tunnel junction or barrier formed by a thin non-magnetic dielectric layer. The magnetic orientation of the free layer can be changed, but the magnetic orientation of the pinned layer remains fixed or “pinned.” Data can be stored in the MTJ according to the magnetic orientation between the free and pinned layers. When the magnetic orientations of the free and pinned layers are anti-parallel (AP) to each other, a first memory state exists (e.g., a logical ‘1’). When the magnetic orientations of the free and pinned layers are parallel (P) to each other, a second memory state exists (e.g., a logical ‘0’). The magnetic orientations of the free and pinned layers can be sensed to read data stored in the MTJ by sensing a resistance when current flows through the MTJ. Data can also be written and stored in the MTJ by applying a magnetic field to change the orientation of the free layer to either a P or AP magnetic orientation with respect to the pinned layer.
Recent developments in MTJ devices involve spin transfer torque (STT)-MRAM devices. In STT-MRAM devices, the spin polarization of carrier electrons, rather than a pulse of a magnetic field, is used to program the state stored in the MTJ (i.e., a ‘0’ or a ‘1’). FIG. 1 illustrates an STT-MTJ device 100. The STT-MTJ device 100 is provided as part of an MRAM bit cell 102 to store non-volatile data. A metal-oxide semiconductor (MOS) (typically n-type MOS, i.e., NMOS) access transistor 104 is provided to control reading and writing to the STT-MTJ device 100. A drain (D) of the access transistor 104 is coupled to a bottom electrode 106 of the STT-MTJ device 100, which is coupled to a pinned layer 108 for example. A word line (WL) is coupled to a gate (G) of the access transistor 104. A source (S) of the access transistor 104 is coupled to a voltage source (VS) through a source line (SL). The voltage source (VS) provides a voltage (VSL) on the source line (SL). A bit line (BL) is coupled to a top electrode 110 of the STT-MTJ device 100, which is coupled to a free layer 112 for example. The pinned layer 108 and the free layer 112 are separated by a tunnel barrier 114.
With continuing reference to FIG. 1, when writing data to the STT-MTJ device 100, the gate (G) of the access transistor 104 is activated by activating the word line (WL). A voltage differential between a voltage (VBL) on the bit line (BL) and the voltage (VSL) on the source line (SL) is applied. As a result, a write current (I) is generated between the drain (D) and the source (S) of the access transistor 104. If the magnetic orientation of the STT-MTJ device 100 in FIG. 1 is to be changed from AP to P, a write current (IAP-P) flowing from the free layer 112 to the pinned layer 108 is generated. This induces a STT at the free layer 112 to change the magnetic orientation of the free layer 112 to P with respect to the pinned layer 108. If the magnetic orientation is to be changed from P to AP, a current (IP-AP) flowing from the pinned layer 108 to the free layer 112 is produced, which induces an STT at the free layer 112 to change the magnetic orientation of the free layer 112 to AP with respect to the pinned layer 108.
As discussed above, a supply voltage can be applied across the MTJ in an MRAM bit cell to generate current for performing write operations. For example, this supply voltage may be a fixed supply voltage applied across an overall circuit and/or chip in which the MRAM is provided. In order to write to the MTJ, a write current (Iw) is generated to equal or exceed the critical switching current (Ic), which is the current required to switch the magnetic orientation of the free layer. In an STT-MTJ device, the Ic required to switch the magnetic orientation of the free layer from P to AP is higher than the Ic required to switch from AP to P. Thus, a higher supply voltage is employed to change the MTJ magnetization state from P to AP than from AP to P in a write operation. If the write current is below the critical switching current (i.e., Iw<Ic), the write current may not be sufficient to switch the state of the MTJ, resulting in a bit error. A bit error is a failed attempt to write the MTJ to an intended state. Since an MTJ is quantum mechanical in nature, the critical switching current is not a single theoretical value, but rather a distribution of values, where the probability of the MTJ switching its state increases as the current flowing across it increases. In order to reduce the risk of bit errors, a designed critical switching current can be selected along the critical switching current curve at a value higher than the theoretical critical switching current. The switching current margin is the difference between the designed critical switching current and the theoretical critical switching current. The design specifications of MRAM bit cells can thus provide a minimum switching current margin to avoid or mitigate erroneous data write operations such as bit errors.
Process variations can cause process corner variations that change the speed at which current flows through the access transistor 104 used to control write operations to the STT-MTJ device 100 in the MRAM bit cell 102 in FIG. 1. For example, process variations can vary the switching speed of the access transistor 104 in the MRAM bit cell 102 in FIG. 1 between typical, typical (TT), fast, fast (FF), and slow, slow (SS). If for example, process variations result in the access transistor 104 having higher impurity levels (i.e., a slow transistor), a higher gate voltage may be required to raise the write current to the designed critical switching current in order to avoid bit errors. However, as voltage increases so does power, which can cause the access transistor 104 to rise in temperature. Such increases in temperature can result in damage to the gate oxide of the access transistor 104 through mechanisms such as breakdown and time-dependent dielectric breakdown. In the opposite case, a fast access transistor 104 can require a lower gate voltage in order to lower the write current to the designed critical switching current. If the supply voltage is not lowered and the designed critical switching current is exceeded, power consumption can become inefficient and the tunnel barrier 114 is overstressed by the write process.
IC designs that include MRAM may employ a fixed supply voltage with a larger corner overhead to cover for process variations that can vary switching current. One disadvantage to providing a larger corner overhead in supply voltage is that switching current margin is increased, which can overstress certain MTJs based on process corner variation and also damage gate oxides of access transistors. This voltage stress can ultimately result in the failure of both MTJs and access transistors. However, if the switching current margin is too low, the switching current may not be sufficient to perform a write operation, thus resulting in increased bit errors and reduced reliability.